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Esame completo di Embedded Systems 1 per il corso di Computer Engineering presso Politecnico di Milano. Materiale proveniente dall’archivio storico Studwiz e classificato per la consultazione online.

Embedded Systems 1Esame completo

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Esame completo di Embedded Systems 1 per il corso di Computer Engineering presso Politecnico di Milano. Materiale proveniente dall’archivio storico Studwiz e classificato per la consultazione online.

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Politecnico di Milano FACOLTÀ DI INGEGNERIA DELL’INFORMAZIONE Sistemi Embedded 1 A.A. 2014-2015 – Exam date: 4 Feb 2015 Prof. William FORNACIARI Surname (readable)........................................ Name (readable)............................ Matr................................................................. Signature........................................ Q1 Q2 Q3 TOT NOTES It is forbidden to refer to texts or notes of any kind as well as interact with their neighbors. Anyone found in possession of documents relating to the course, although not directly relevant to the subject of the examination will cancel the test. It is not allowed to leave during the first half hour, the task must still be returned, even if it is withdrawn. The presence of the writing (not delivered) implies the renunciation of any previous ratings. Question Q1 (10 points) Which are the main differences between a real and an ideal sensor? Considering a MEMS inertial sensors tailored to measures accelerations, which are the most relevant aspects differentiating such solution to other available technologies? 1/7 2/7 Question Q2 a) (5 points) Consider an on-chip bus interconnect with support for pipeline transactions used for communicate between the CPUs and the memory. Discuss the main limitations of such architecture in terms of bus utilization and overall system performance. Then describe the split transaction and burst transaction optimizations and how they can face such limitations. (Synthetic examples may help the answer, while cannot substitute the discussion). SHORT SOLUTION The standard pipelined bus architecture grants the bus to a transaction keeping it reserved until the end of the transaction. Since, all the transactions, i.e. reads and writes, requires access to memory, the…

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