← Indietro
EsameEsame completoTesto d’esame

06 07 16 2

Esame completo di Digital Systems Design Methodologies per il corso di Computer Engineering presso Politecnico di Milano. Materiale proveniente dall’archivio storico Studwiz e classificato per la consultazione online.

Digital Systems Design MethodologiesEsame completo

Informazioni sul documento

Cosa trovi in questo materiale

Esame completo di Digital Systems Design Methodologies per il corso di Computer Engineering presso Politecnico di Milano. Materiale proveniente dall’archivio storico Studwiz e classificato per la consultazione online.

Qualità dell’importazione: il testo è stato estratto direttamente dal documento originale.

Contenuti estratti dal documento

Passaggi rappresentativi riconosciuti nelle diverse parti del materiale. Il testo completo resta presente nella pagina per la ricerca, mentre l’anteprima compatta rende più semplice la lettura.

Pagina 1

Politecnico di Milano Dipartimento di Elettronica, Informazione e Bioingegneria prof. Fabrizio Ferrandi Digital Systems Design Methodologies 1 – July 6th 2016 Polimi ID _______ _______________________ Surname _______ __________________ Name _____________________  This is a closed -book examination. You cannot use computers, phones or laptops during the exam.  Paper will be provided, but you should bring and use writing instruments that yield marks dark enough to be read easily. Erasable pens can be used.  Total available time: 1h:45m. Exercise 1 (6 points) _________________________ Exercise 2 (5 points) _________________________ Exercise 3 (6 points) _________________________ Exercise 4 (5 points) _________________________ Exercise 5 (6 points) _________________________ Exercise 6 (5 points) _________________________ Digital Systems Design Methodologies 1 – July 6th 2016 2 /14 Exercise n. 1 Given the following circuit: and the following technology library: a) Build the subject graph and determine the formulation of the binate covering problem for the technology mapping targeting area minimization. b) Identify one feasible solution (not necessarily the optimal one) using the DAGON heuristic. Digital Systems Design Methodologies 1 – July 6th 2016 3 /14 Digital Systems Design Methodologies 1 – July 6th 2016 4 /14 Exercise n. 2 Given the following circuit where the delay of the OR, XOR, and AND gates is equal to 2, while the delay of the inverters is equal to 1. a) Compute the circuit delay given these values applied to the inputs: A=0, B=1, C=0, D=0, E=0. b) Verify if C-F-G-I-L-OUT is a false path and apply KMS Digital Systems Design Methodologies 1 – July 6th 2016 5 /14

Anteprima

Prima pagina del documento.

Prima pagina: 06 07 16 2