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Course on Advanced Computer Architectures Surname (Cognome) SOLUTION Name (Nome) POLIMI ID Number Signature (Firma) Politecnico di Milano, September 7th, 2016 Prof. C. Silvano EX1A ( 2 points) EX1B ( 2 points) EX1C ( 2 points) EX2 ( 5 points) EX3 ( 5 points) Subtotal ( 16 points) Q4 ( 5 points) Q5 ( 6 points) Q6 ( 5 points) TOTAL (32 points) Course on: Advanced Computer Architectures – Prof. C Silvano EXAM 07/09/2016 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) Page 1 - SOLUTION EXERCISE 1A – PIPELINE BASIC (2 points) Given the following program has been compiled in MIPS assembly code assuming that registers $t6 and $t7 have been initialized with values 0 and 4N respectively. The symbols VECTA and VECTB are 16-bit constant. The processor clock frequency is 1 GHz. Let us consider the loop executed by 5- stage pipelined MIPS processor WITHOUT any optimization in the pipeline (PLEASE don’t consider any inter-iteration dependencies) 1. Identify the RAW (Read After Write) Hazards in the pipeline scheme and identify the Hazard Type (Data Hazard or Control Hazard) in the last column 2. Identify in the first column the number of stalls to be inserted before each instruction (or between the stage IF and ID of each instruction) necessary to solve the hazards Num. Stalls INSTRUCTION C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 Hazard Type 3 FOR:lw $t1,VECTA($t6) IF ID EX ME WB CNTR lw $t2,VECTB($t6) I F I D E X M E W B 3 add $t5,$t2,$t1 I F I D E X M E W B (RAW $t1) RAW $t2 3 lw $t3,0($t5) I F I D E X M E W B R A W $ t 5 lw $t4,VECTC($t6) I F I D E X M E W B 3 or $t3,$t3,$t4 I F I D E X M E W B (RAW $t3) RAW $t4 3 sw $t3,0($t5) I F I D E X M E W B R A W $ t 3 addi $t6,$t6,4 I F I D E X M E W B 3 blt $t6,$t7, FOR I F I D E X M E W B RAW…