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Esame completo di Digital Systems Design Methodologies per il corso di Computer Engineering presso Politecnico di Milano. Materiale proveniente dall’archivio storico Studwiz e classificato per la consultazione online.

Digital Systems Design MethodologiesEsame completo

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Esame completo di Digital Systems Design Methodologies per il corso di Computer Engineering presso Politecnico di Milano. Materiale proveniente dall’archivio storico Studwiz e classificato per la consultazione online.

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Politecnico di Milano Dipartimento di Elettronica e Informazione prof. Fabrizio Ferrandi Digital Systems Design Methodologies 1 – September 8th 2016 Polimi ID _______ _______________________ Surname _______ __________________ Name _____________________  This is a closed -book examination. You cannot use computers, phones or laptops during the exam.  Paper will be provided, but you should bring and use writing instrum ents that yield marks dark enough to be read easily. Erasable pens can be used.  Total available time: 1h:45m. Exercise 1 (5 points) _________________________ Exercise 2 (6 points) _________________________ Exercise 3 (6 points) _________________________ Exercise 4 (5 points) _________________________ Exercise 5 (6 points) _________________________ Exercise 6 (5 points) _________________________ Digital Systems Design Methodologies 1 – September 8th 2016 2 /9 Exercise n. 1 Given the following circuit: and the following technology library: a) Build the subject graph and determine the formulation of the binate covering problem for the technology mapping targeting area minimization. b) Identify one feasible solution (not necessarily the optimal one) using the DAGON heuristic. c) Check that the solution obtained by the DAGON heuristic satisfies the formulation of the binate covering problem. Digital Systems Design Methodologies 1 – September 8th 2016 3 /9 Digital Systems Design Methodologies 1 – September 8th 2016 4 /9 Exercise n. 2 Given the following circuit: where the delay of the OR and AND gates is equal to 2, while the delay of the inverters is equal to 1. a) Compute the circuit delay given these values applied to the inputs: A=1, B=0, C=1, D=1. b) Check with the proper algorithm if the output OUT is stable at time T=7 Digital Systems Design…

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