09 06 2021 E T Santambrogio

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Dipartimento di Elettronica e Informazione Politecnico di Milano 20133 Milano (Italia) Piazza Leonardo da Vinci, 32 Tel. (+39) 02-2399.3400 Fax (+39) 02-2399.3411 Advanced Computer Architecture June 09, 2021 Prof. Marco Santambrogio Name Last Name Pick 2 out of th 3 problems, DO NOT DO ALL THE 3! Questions (from Forms) (20%) Problem 1 (40%) Problem 2 (40%) Problem 3 (40%) Total (100%) Problem 1 Assume that the following code is executed on a CPU with SCOREBOARD and with the following units: 1 LOAD/STORE unit with Latency= 1 2 MULT units with latency = 10 1 DIVIDE unit with latency = 30 1 ADD/SUBD unit with latency 2 Issue Read Op Exec Co. Write R. LD F6 32+ R2 1 2 3 4 LD F2 45+ R3 5 6 7 8 MULTD F0 F4 F2 6 9 19 20 ADD F8 F2 F6 7 9 10 11 DIVD F12 F8 F0 8 21 51 52 SUBD F8 F6 F2 9 13 14 15 A. List all the possible conflicts in the code. B. Is there a “configuration” that can respect the shown execution? How many units? Which kind? What latency? C. If the previous table was not correct, please, write the right one by having: 1 LOAD: 1cc 2 MULT: 10cc 1 DIVL 30cc 3 ADD/SUB: 1cc Answer 1.A 1 LDU 1 CC 2 MULT 10 1 DIV 30 1 ADD/SUB 2 RAW F6 I1-I4 RAW F6 I1-I6 RAW F2 I2-I3 RAW F2 I2-I4 RAW F2 I2-I6 RAW F0 I3-I5 RAW F8 I4-I5 WAR F8 I5-I6 WAW F8 I4-I5 Answer 1.B Answer 1.C Issue Read Op Exec Co. Write R. LD F6 32+ R2 LD F2 45+ R3 MULTD F0 F4 F2 ADD F8 F2 F6 DIVD F12 F8 F0 SUBD F8 F6 F2 1 2 3 4 5 6 7 8 6 9 7 9 19 10 20 11 8 21 51 52 12 13 14 22 No for several reasons, among which WAW and WAR unsolved, and the given latency of the FU is not respected. One of those is enough to say that no. Problem 2 Consider the following access pattern on a two-processor system with a direct-mapped, write-back cache with one cache block and a two cache block memory. Assume the MESI protocol is used,…