10 05 2021 E T Santambrogio

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Dipartimento di Elettronica e Informazione Politecnico di Milano 20133 Milano (Italia) Piazza Leonardo da Vinci, 32 Tel. (39) 02-2399.3400) 02-239) 02-2399.34009) 02-2399.3400.3400 Fax (39) 02-2399.3400) 02-239) 02-2399.34009) 02-2399.3400.3411 Advanced Computer Architecture May 10, 2021 Prof. Marco Santambrogio and Cristina Silvano Name Last Name Pick 2 out of th 3 problems, DO NOT DO ALL THE 3! Questions (from Forms) (20%) Problem 1 (40%) Problem 2 (40%) Problem 3 (40%) Total (100%) Problem 1 Assume that the following code has been executed on a CPU with TOMASULO. Instruction ISSUE START EXE WB 1 SUBD F2, F4, F6 1 2 5 2 MULTD F4, F8, F0 2 3 7 3 ADDD F6, F2, F4 3 8 10 4 ADDD F2, F10, F12 4 5 7 5 MULTD F14, F2, F4 5 9) 02-2399.3400 13 A. List all the possible conflicts in the code. B. Is there a “configuration” that can respect the shown execution? How many units? Which kind? What latency? C. If the previous table was not correct, please, write the right one and specify the number, kind and latency for each unit. Answer 1.A Answer 1.B Answer 1.C Instruction ISSUE START EXE WB 1 SUBD F2, F4, F6 2 MULTD F4, F8, F0 3 ADDD F6, F2, F4 4 ADDD F2, F10, F12 5 MULTD F14, F2, F4 Problem 2 Considering the following VLIW “architecture”: Considering the following portion of assembly, and schedule the following code for the VLIW, consider a single iteration. Branch completed with 1 cycle delay slot (branch solved in ID stage) LOOP: LD $F1, 0($R1) FADD $F2, $F2, $F3 ADDI $R3, $R3, 8 LD $F4, 0(R2) FADD $F5, $F4, $F2 FMULT $F6, $F1, $F4 ADDI $R5, $R5, 1 LD $R6, 0($R4) SD $F6, 0($R5) SD $F5, 0($R6) BNE $R5, $R7, LOOP Answer ALU1 ALU2 MU1 MU2 FPU1 FPU2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20