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Course on Advanced Computer Architectures Surname (Cognome) SOLUTION Name (Nome) POLIMI ID Number Signature (Firma) Politecnico di Milano, July 12th, 2016 Prof. C. Silvano EX1A ( 2 points) EX1B ( 2 points) EX2A ( 4 points) EX2B ( 4 points) EX3 ( 4 points) Subtotal ( 16 points) Q4 ( 5 points) Q5 ( 6 points) Q6 ( 5 points) TOTAL (32 points) Advanced Computer Architectures – Prof. C Silvano EXAM 12/07/2016 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! Page 2 - SOLUTION EXERCISE 1A – PIPELINE BASIC (2 points) Given the following loop expressed in a high-level language: for (j = 0, i = 1; i < N; i++, j++) ^ vectA[i] = vectB[j] + k; vectC[i] = vectC[j]; ` The program has been compiled in MIPS assembly code assuming that registers $t6, and $t7 have been initialized with values 0 and 4 respectively. The symbols vectA, vectB, and vectC are 16-bit constant. The processor clock frequency is 1.2 GHz. Let us consider the loop executed by 5-stage pipelined MIPS processor WITHOUT any optimization in the pipeline (PLEASE don’t consider any inter-iteration dependencies) 1. Identify the RAW (Read After Write) Hazards in the pipeline scheme and identify the Hazard Type (Data or Control Hazard) in the last column 2. Identify in the first column the number of stalls to be inserted before each instruction (or between the IF and ID stage of each instruction) to solve the hazards blt $t7, $t8, FOR # branch on less than, x Number of stalls per iteration: Nstall = 14 _______________ x Asymptotic CPI (N cycles) : CPI AS= (IC + # stalls) / IC = (8+14) /8 = 2.75___________________________________ Num. Stalls INSTRUCTION C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 Hazard Type 3 FOR: lw $t2,VECTB($t6)IF ID EX ME WB C N T R 3 addi $t3,$t2,k I F ID EX ME WB RAW $t2 3 s w $ t 3 , V E C T A ( $…