15 07 2024 E S Silvano

Pagina 1

Surname (COGNOME) SOLUTION Name POLIMI Personal Code Signature Politecnico di Milano, 15 July, 2024 Course on Advanced Computer Architectures Prof. C. Silvano EX1 ( 5 points) EX2 ( 5 points) EX3 ( 5 points) Q1 ( 5 points) Q2 ( 5 points) QUIZZES ( 8 points) TOTAL (33 points) Course on Advanced Computer Architectures – prof. C. Silvano EXAM 15 July 2024 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! Page 1 - SOLUTION EXERCISE 1 – DEPENDENCY ANALYSIS + TOMASULO (5 points) 1. Let’s consider the following assembly code containing multiple types of intra-loop dependences. Complete the following table by inserting all types of true-data-dependences, anti-dependences and output dependences for each instruction: I# TYPE OF INSTRUCTION ANALYSIS OF DEPENDECES: 1. True data dependence with I# for $Fx 2. Anti-dependence with I# for $Fy 3. Output-dependence with I# for $Fz I0 FOR:LD $F2, A($R1) None I1 FADD $F2, $F2, $F2 True data dependence with I0 for $F2 Output data dependence with I0 for $F2 I2 FADD $F2, $F2, $F4 True data dependence with I1 for $F2 Output data dependence with I1 for $F2 Anti-dependence with I1 for $F2 I3 SD $F2, A($R1) True data dependence with I2 for $F2 I4 ADDUI $R1, $R1, 8 Anti dependence with I0 for $R1 Anti dependence with I3 for $R1 I5 BNE $R1, $R2, FOR True data dependence with I4 for $R1 Let’s consider the previous assembly code to be executed on a CPU with dynamic scheduling based on TOMASULO algorithm with all cache HITS, a single Common Data Bus and: • 2 RESERV. STATIONS (RS1, RS2) with 2 LOAD/STORE units (LDU1, LDU2) with latency 4 • 2 RESERVATION STATION (RS3, RS4) with 1 FP unit1 (FPU1) with latency 3 • 2 RESERVATION STATION (RS5, RS6) with 1 INT_ALU/BR unit (ALU1) with latency 2 Please complete the following table: INSTRUCTION ISSUE…