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Surname (Cognome) SOLUTION Name (Nome) POLIMI ID Number Signature (Firma) Politecnico di Milano, January 18, 2019 Course on Advanced Computer Architectures Prof. D. Sciuto, Prof. C. Silvano EX1 ( 5 points) EX2 ( 6 points) EX3 ( 5 points) Q1 ( 5 points) Q2 ( 5 points) SIX QUESTIONS ( 6 points) TOTAL (32 points) Course on Advanced Computer Architectures EXAM 18/01/2018 – Please write by PEN in CAPITAL LETTERS & BLACK/BLUE!!! Page 1 - SOLUTION EXERCISE 1 – MULTI-CYCLE PIPELINE (5 points) In this problem we will examine the execution of the following code segment on the following single-issue out-of-order processor:  All functional units are pipelined  ALU operations take 1 clock cycle  Memory operations take 2 clock cycles (includes time in ALU)  FP ADD operations take 1 clock cycles, FP MUL operations take 2 clock cycles  The Write Back unit has a single write port  There is no register renaming  Instructions are fetched, decoded and issued in order  An instruction will only enter the ISSUE stage if it does not cause a WAR or WAW hazard  Only one instruction can be issued at a time, and in the case m ultiple instructions are ready, the oldest one will go first Fill in the following table pointing out, for each instruction, the pipeline stages activated in each clock cycle and type of hazards: Instruction C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 Type of Hazards lw.d $f3,BASEA($r1) IF ID IS ALU ME WB lw.d $f4,BASEB($r1) IF ID IS ALU ME WB mul.d $f3,$f3,$f4 IF ID IS FM1 FM2 WB RAW $f4, RAW $f3, WAW $f3 add.d $f4,$f4,$f3 IF ID IS FA1 WB RAW$f4 RAW $f3, WAW $f4, struct WB sw.d $f4,BASEC($r1) IF ID IS ALU ME WB RAW $f4 Insert in the empty pipeline scheme the pipeline stages and stalls needed to solve the previous data, control and structural hazards. INS C1 C2 C3 C4 C5 C6 C7 C8…