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Advanced Computer Architectures July 18, 2017 Prof. Donatella Sciuto Name Last Name POLIMI ID Number Problem 1 (5 points) Problem 2 (5 points) Problem 3 (6 points) Question 1 (5 points) Question 2 (6 points) Question 3 (5 points) Total (32 points) Problem 1 In this problem, you will port code to a simple VLIW machine, and modify it to improve performance. Details about the VLIW machine: • Three fully pipelined functional units (Integer ALU, Memory, and Floating Point) • Integer ALU has a 1 cycle latency • Memory Unit has a 3 cycle latency • FPU has a 3 cycle latency and can complete one add or one multiply (but not both) per clock cycle • No interlocks C Code: Assembly Code: for(int i=0; i<N; i++) C[i] = A[i]*A[i] + B[i]; loop: ld f1, 0(r1) ld f2, 0(r2) fmul f1, f1, f1 fadd f1, f1, f2 st f1, 0(r3) addi r1, r1, 4 addi r2, r2, 4 addi r3, r3, 4 bne r3, r4, loop Problem 3.A Schedule operations into the VLIW instructions in the following table. Show only one iteration of the loop. Make the code efficient, but do not use software pipelining or loop unrolling. You do not need to write in NOPs (can leave blank). ALU Memory Unit FPU What performance did you achieve? (in FLOPS per cycle):_________ Problem 3.B Unroll the loop by one iteration (so two iterations of the original loop are performed for every branch in the new assembly code). You only need to worry about the steady-state code in the core of the loop (no epilogue or prologue). Make the code efficient, but do not use software pipelining. You do not need to write in NOPs (can leave blank). ALU Memory Unit FPU What performance is achieved now? (in FLOPS per cycle): _________ Problem 2 Assume that the following code has been executed on a CPU with SCOREBOARD (no ROB). Issue Read Op Exec Co. Write R. I1: LD F6 32+ R2 1 2 7…