19 06 2024 E T Pilato

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Dipartimento di Elettronica e Informazione Politecnico di Milano 20133 Milano (Italia) Piazza Leonardo da Vinci, 32 Tel. (+39) 02-2399.3400 Fax (+39) 02-2399.3411 Advanced Computer Architectures June 19, 2024 Prof. Christian Pilato Name Last Name ID Number Problem 1 (20%) Problem 2 (15%) Problem 3 (15%) Question 1 (15%) Question 2 (20%) Question 3 (15%) Total (100%) NOTE: students have 90’ to complete the exam. To pass the exam, a minimum score of 25% is requested by each “section” (section 1: problems, section 2: questions). Problem 1 In this problem, you will port code to a simple 4-issue VLIW machine, and schedule it to improve performance. Details about the 4-issue VLIW machine with 4 fully pipelined functional units: • Integer ALU with 1 cycle latency to next Integer/FP and 2 cycle latency to next Branch • Memory Unit with 3 cycle latency • Floating Point Unit with 3 cycle latency (each FPU can complete one add or one multiply per clock cycle) • Branch completed with 1 cycle delay slot (branch solved in ID stage) Assembly Code: Bb0: ld $1, 24($R1) ld $2, 8($R1) ld $3, 4($R1) addd $2, $2, $3 addd $1, $1, $2 addi $R1 $R1 4 sd $1, 16($fp) bnez $R1, BB0 P1.A Considering one iteration of the loop, schedule the assembly code for the 4-issue VLIW machine in the following table by using the list-based scheduling, but neither using software pipelining nor loop unrolling nor modifying loop indexes. Please do not need to write in NOPs (can leave blank). P1.B Answer the following performance questions How long is the Critical Path? What performance did you achieve in FP ops per cycle? Answer 1.A ALU 1 cc MEM 2 cc MEM 2 cc FPU 5cc C1 ld $1, 24($R1) ld $2, 8($R1) C2 addi $R1 $R1 4 ld $3, 4($R1) C3 C4 addd $2, $2, $3 C5 C6 C7 C8 C9 addd $1, $1, $2 C10 C11 C12 C13 C14 bnez $R1,…