19 06 2024 E TS Silvano

Pagina 1

Surname (COGNOME) SOLUTION Name POLIMI Personal Code Signature Politecnico di Milano, 19 June, 2024 Course on Advanced Computer Architectures Prof. C. Silvano EX1 ( 5 points) EX2 ( 5 points) EX3 ( 5 points) Q1 ( 4 points) Q2 ( 6 points) QUIZZES ( 8 points) TOTAL (33 points) Course on Advanced Computer Architectures – prof. C. Silvano EXAM 19 June 2024 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! Page 1 - SOLUTION EXERCISE 1 – SCOREBOARD (5 points) 1. Let’s consider the following assembly code containing multiple types of intra-loop dependences. Complete the following table by inserting all types of true-data-dependences, anti-dependences and output dependences for each instruction: I# TYPE OF INSTRUCTION ANALYSIS OF DEPENDECES: 1. True data dependence with I# for $Fx 2. Anti-dependence with I# for $Fy 3. Output-dependence with I# for $Fz I0 LOOP: LD $F2, 0($R1) None I1 LD $F4, 0($R2) None I2 FADD $F4,$F2,$F4 True data dependence with I0 for $F2 True data dependence with I1 for $F4 Output dependence with I1 for $F4 I3 SD $F4,0($R1) True data dependence with I2 for $F4 I4 ADDUI $R1,$R1,4 Anti dependence with I0 for $R1 Anti dependence with I3 for $R1 I5 ADDUI $R2,$R2,4 Anti dependence with I1 for $R2 I6 BNE $R1,$R3,LOOP True data dependence with I4 for $R1 Course on Advanced Computer Architectures – prof. C. Silvano EXAM 19 June 2024 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! Page 2 - SOLUTION 2. Schedule the code on a CPU with dynamic scheduling based on OPTIMIZED SCOREBOARD with the following assumptions: • 2 LOAD/STORE Units (LDU1, LDU2) with latency 3 cycles • 1 FP Unit (FPU1) with latency 4 cycles • 2 ALU/BR Units (ALU1, ALU2) with latency 1 cycle • Register File with 2 read ports and 1 write port • Check for WAR and WAW hazards…