21 06 2021 E TS Santambrogio

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Dipartimento di Elettronica e Informazione Politecnico di Milano 20133 Milano (Italia) Piazza Leonardo da Vinci, 32 Tel. (39) 02-2399.3400) 02-239) 02-2399.34009) 02-2399.3400.3400 Fax (39) 02-2399.3400) 02-239) 02-2399.34009) 02-2399.3400.3411 Advanced Computer Architecture June 21, 2021 Prof. Marco Santambrogio Name Last Name Code Name (Codice Persona) WRITE YOUR NAME and CODE NAME. Pick 2 out of th 3 problems, DO NOT DO ALL THE 3! Questions (from Forms) (20%) Problem 1 (40%) Problem 2 (40%) Problem 3 (40%) Total (100%) Problem 1 Consider the following VLIW “architecture” with multi-cycled unpipelined functional units. Considering the following portion of assembly. LOOP: beq $t6,$t7, END lw $t2,VECTB($t6) lw $t3,VECTC($t6) sw $t2,VECTA($t6) addi $t3,$t3,4 sw $0,VECTD($t6) sw $t3,VECTC($t6) addi $t6,$t6,4 blt $t6,$t7, LOOP 1.A schedule the following code for the VLIW with an IN-ORDER ISSUE. Branch completed with 1 cycle delay slot (branch solved in ID stage). 1.B How the does the scheduling change if we consider an IN-ORDER ISSUE and pipelined FU? Answer 1.A Postponing by two CC for control hazard has been considered correct as well Answer 1.B Problem 2 In this problem we will examine the execution of a code segment on the following single-issue out-of-order processor: You can assume that:  All functional units are pipelined  ALU operations take 1 cycle  MEM operations take 3 cycles (includes time in ALU)  FP add instructions take 3 cycles  FP multiply instructions take 5 cycles  The WB unit has a single write port.  RF can write first half of the CC and Read in the second half.  There is no register renaming  Instructions are fetched, decoded and issued in order  The issue stage is a buffer of unlimited length that holds instructions waiting to start…