21 07 2022 E S Santambrogio

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Dipartimento di Elettronica e Informazione Politecnico di Milano 20133 Milano (Italia) Piazza Leonardo da Vinci, 32 Tel. (+39) 02-2399.3400 Fax (+39) 02-2399.3411 Advanced Computer Architecture July 21, 2022 Prof. Donatella Sciuto and Marco Santambrogio Name Last Name Professor: You have 90’ to complete the exam Problem 1 (6pts) Problem 2 (6pts) Problem 3 (6pts) Question 1 (5pts) Question 2 (5pts) Question 3 (5pts) Total (32pts) To pass the exam (the following conditions are in AND): • The overall score has to be equal or higher than 18 • At least 1 problem and 1 Question has to be correct Problem 1 Consider two CPUs: CPU1 e CPU2. CPU1 has clock cycle of 2 ns while CPU2 has an operating frequency of 700MHz. Given the following frequencies of occurrence of the instructions for the two CPUs Operation type Frequency CPU1 CPU2 A 0.3 2 2 B 0.1 3 3 C 0.2 4 3 D 0.3 2 2 E 0.1 4 3 a) Compute the average CPI for CPU1 and CPU2 b) Which is the slowest CPU? c) Assume that CPU1 is modified in such a way that: • All instructions require 8 clock cycles; • Memory stalls are not considered; • The miss penalty is 7 clock cycles Assuming a miss rate of 23% and assuming 3 memory references on average for each instruction determine the impact on performance of the cache with respect to an ideal cache? Answer a) CPI–CPU1 = 0.3*2 + 0.1*3 + 0.2*4 + 0.3*2 + 0.1*4 = 0.6+0.3+0.8+0.6+0.4 = 2.7 CPI–CPU2 = 0.3*2 + 0.1*3 + 0.2*3 + 0.3*2 + 0.1*3 = 0.6+0.3+0.6+0.6+0.3 = 2.4 b) Speedup = Exe-CPU1/Exe-CPU2 = = ((IC * CPI1)/Freq1)*(Freq2/(IC * CPI2)) = = (IC * CPI1 * Freq2)/(IC * CPI2 * Freq1) = = (CPI1*Freq2)/(CPI2 * Freq1) = = (2.7 * 700MHz)/(2.4 * 500MHz) = 1890/1200 = 1.575 c) CPI_exe = 8; MISS Penalty = 7; MISS Rate = 0.23; Memory references = 3 CPI_ideal_cache (MISS Rate = 0) = 8 CPI_cache =…