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Course on Advanced Computer Architectures Surname (Cognome) SOLUTION Name (Nome) POLIMI ID Number Signature (Firma) Politecnico di Milano, September 21st, 2016 Prof. C. Silvano EX1 ( 6 points) EX2 ( 4 points) EX3 ( 6 points) Subtotal ( 16 points) Q4 ( 5 points) Q5 ( 6 points) Q6 ( 5 points) TOTAL (32 points) Course on: Advanced Computer Architectures – Prof. C Silvano EXAM 21/09/2016 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) Page 1 - SOLUTION EXERCISE 1 – MULTI-CYCLE PIPELINE (6 points) In this problem we will examine the execution of a code segment on the following single-issue out-of-order processor: You can assume that:  All functional units are pipelined  ALU operations take 1 cycle  Memory operations take 3 cycles (includes time in ALU)  Floating-point add instructions take 3 cycles  Floating-point multiply instructions take 5 cycles  The Write Back unit has a single write port  There is no register renaming  Instructions are fetched, decoded and issued in order  The issue stage is a buffer of unlimited length that holds instructions waiting to start execution  An instruction will only enter the issue stage if it does not cause a WAR or WAW hazard  Only one instruction can be issued at a time, and in the case multiple instructions are ready, the oldest one will go first IF ID ISSUE ALU MEM FADD FADD FMUL WB Course on: Advanced Computer Architectures – Prof. C Silvano EXAM 21/09/2016 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) Page 2 - SOLUTION Fill in the following table pointing out, for each instruction, the pipeline stages activated in each clock cycle, the type of hazards and the number of stalls to be inserted to solve the hazards. INSTRUCTION C1 C2 C3…