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25 06 2020 E T Santambrogio

Esame completo di Advanced Computer Architectures per il corso di Computer Engineering presso Politecnico di Milano. Materiale proveniente dall’archivio storico Studwiz e classificato per la consultazione online.

Advanced Computer ArchitecturesEsame completo

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Esame completo di Advanced Computer Architectures per il corso di Computer Engineering presso Politecnico di Milano. Materiale proveniente dall’archivio storico Studwiz e classificato per la consultazione online.

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Dipartimento di Elettronica e Informazione Politecnico di Milano 20133 Milano (Italia) Piazza Leonardo da Vinci, 32 Tel. (+39) 02-2399.3400 Fax (+39) 02-2399.3411 Advanced Computer Architecture June 25, 2020 Prof. Marco Santambrogio Name Marco && Davide Last Name Santambrogio && Conficconi The student has to choose 2 out of the 3 exercises. If all the 3 exercises will be completed, just the 2 with the lowest score will be considered. This is an open book exam, which means the students can you use all their notes (we do not care of the format) but they cannot share their exams with anyone during the test. At the end of the exam, when the professor will call it, each student has to upload 1 PDF file (named using the “codice persona” – CodicePersona.pdf) using the Microsoft Form share via the Zoom chat at the beginning of the exam. In the first page of the uploaded PDF, the professor has to find the name and the surname of the student. Problem 1 (50%) Problem 2 (50%) Problem 3 (50%) Total (100%) Problem 1 Question1 - To implement cache coherency one of the protocols is the MESI concurrency protocol implemented for a write-invalidate write-back cache. Describe briefly the algorithm (also in term of graph) and complete the following table. State Cache up to date? Memory up to date? Others have a copy? Cache can respond other’s reads? Modified Yes No No Yes Exclusive Yes Yes No Yes Shared Yes Yes yes No Invalid No Maybe Maybe No Question 2 - Consider the following access pattern on a two-processor system with a direct-mapped, write-back cache with one cache block and a two cache block memory. Assume the MESI protocol is used, with write-back caches, and invalidation of other caches on write (instead of updating the value in the other caches). NOTE: you can recreate the table…

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