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Dipartimento di Elettronica e Informazione Politecnico di Milano 20133 Milano (Italia) Piazza Leonardo da Vinci, 32 Tel. (+39) 02-2399.3400 Fax (+39) 02-2399.3411 High Performance Processors and Systems June 27, 2016 Prof. Donatella Sciuto Name: Surname: UID (aka #Matricola) Problem 1 (20%) Problem 2 (30%) Question 1 (20%) Question 2 (10%) Question 3 (20%) Total (100%) NOTE: to pass the midterm, a minimum score of 25% is requested by each “section” (section 1: problems, section 2: questions). Problem 1 Assume that the following code is executed on a CPU with dynamic scheduling based on TOMASULO and with the following units: • the LOAD queue has 3 reservation stations with latency equal to 2 • the STORE queue has 2 reservation stations with Latency equal to 2 • two ADD/SUBD units with latency equal to 3 • two MUL units with latency equal to 5 • an integer unit Assume static branch prediction backward taken and forward not taken. Problem 1.A Consider the following code and schedule the first iteration of the loop for the floating point unit. Loop: LD F0 0(R1) LD F2 -8(R1) ADDD F4 F0 F2 MULD F4 F4 #8 SUBI R1 R1 #16 BNEZ R1 Loop Answer 1.A Issue Exec Co. Write R. LD F0 0(R1) LD F2 -8(R1) ADDD F4 F0 F2 MULD F4 F4 #8 SUBI R1 R1 #16 BNEZ R1 Loop Problem 1.B Given the architecture described how many loop iterations can be overlapped? Does this code stall for structural hazards? Answer 1.B Problem 2 Problem 2.A To implement cache coherency one of the protocols is the MESI concurrency protocol implemented for a write-invalidate write-back cache. Describe briefly the algorithm (also in term of graph) and complete the following table. Answer 2.A State Cache up to date? Memory up to date? Others have a copy? Cache can respond other’s reads? Modified Exclusive Shared Invalid Problem…