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Advanced Computer Architectures June 27, 2016 Prof. Donatella Sciuto Name Last Name Student id Problem 1 (6 points) Problem 2 (5 points) Problem 3 (6 points) Question 1 (5 points) Question 2 (5 points) Question 3 (5 points) Total (32 points) Problem 1 In this problem we will examine the execution of a code segment on the following single-issue out-of-order processor: You can assume that: • All functional units are pipelined • ALU operations take 1 cycle • Memory operations take 3 cycles: 1 clock cycle for the ALU and 2 clock cycles for memory operation. It is possible to start the ALU operation of the load or store if a previous memory operation is in the MEM stage. • Floating-point add instructions take 3 cycles • Floating-point multiply instructions take 5 cycles • There is no register renaming • Instructions are fetched, decoded and issued in order • The issue stage is a buffer of unlimited length that holds instructions waiting to start execution • An instruction will only enter the issue stage if it does not cause a WAR or WAW hazard • Only one instruction can be issued at a time, and in the case multiple instructions are ready, the oldest one will go first • WB stage has only one write port, if multiple operations conclude execution in the same clock cycle, write-back will occur in the order of issue. To simplify book-keeping for this problem we will only track instructions during a few critical stages: • I - When an instruction enters the issue stage • E - When an instruction starts execution (enters FU) • C - When an instruction completes execution and enters WB, the results are available this cycle for reading IF ID ISSUE ALU MEM FADD FADD FMUL WB For this problem we will be using the following code: I1 L.D F2, 0(R1) I2 ADD.D F1, F1, F2 I3 L.D F4, 0(R2) I4…