29 06 2022 E T Santambrogio

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Dipartimento di Elettronica e Informazione Politecnico di Milano 20133 Milano (Italia) Piazza Leonardo da Vinci, 32 Tel. (+39) 02-2399.3400 Fax (+39) 02-2399.3411 Advanced Computer Architecture June 29, 2022 Prof. Donatella Sciuto and Marco Santambrogio Name Last Name Professor: You have 90’ to complete the exam Problem 1 (6pts) Problem 2 (6pts) Problem 3 (6pts) Question 1 (5pts) Question 2 (5pts) Question 3 (5pts) Total (32pts) To pass the exam (the following conditions are in AND): • The overall score has to be equal or higher than 18 • At least 1 problem and 1 Question has to be correct Problem 1 Design and describe (all the decisions have to be motivated) a 1-BHT and a 2-BHT able to execute the following assembly code. (R0 is set to 100, R1 is set to 0) LOOP: LD F3 0 R0 ADDD F1 F3 F3 MULTD F2 F3 F1 ADDI R1 R1 1000 LOOP2: LD F3 0 R1 MULTD F2 F2 F3 SUBI R1 R1 10 BNEZ R1 LOOP2 SUBI R0 R0 10 BNE R0 R1 LOOP The obtained result, in terms of miss predictions, is inline with theoretical characteristics of the two predictors? Please effectively support your answer. Answer LOOP 10 times, LOOP2 steady 100 Worst case: 1BHT, not colliding initialized with NT and NT. 1+1 misprediction for LOOP and (1+1) * 10 for LOOP2. Total of 22 miss. 2BHT, NT strong and NT strong. 2 + 1 misprediction@LOOP and 2 + (1)*10@LOOP2. Total of 15 miss. Best case: 1BHT. T and T: 1@LOOP and 1 + 2*9@LOOP2. Total of 20 miss. Best of 1BHT is worst than worst-case of 2BHT Problem 2 In this problem we will examine the execution of a code segment on the following single-issue out-of-order processor: You can assume that: • All functional units are pipelined • ALU operations take 1 cycle • Memory operations take 3 cycles (includes time in ALU) • Floating-point add instructions take 3 cycles • Floating-point…