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Course on Advanced Computer Architectures Surname (Cognome) SOLUTION Name (Nome) POLIMI ID Number Signature (Firma) Politecnico di Milano, June 30th, 2017 Prof. C. Silvano EX1 ( 6 points) EX2 ( 5 points) EX3 ( 5 points) Q1 ( 5 points) Q2 ( 6 points) Q3 ( 5 points) TOTAL (32 points) Course on: Advanced Computer Architectures – Prof. C Silvano EXAM 30/06/2017 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) Page 1 - SOLUTION EXERCISE 1 – MULTI-CYCLE PIPELINE (6 points) In this problem we will examine the execution of a code segment on the following single-issue out-of-order processor: You can assume that:  All functional units are pipelined  ALU operations take 1 cycle  Memory operations take 3 cycles (includes time in ALU)  The Write Back unit has a single write port  There is no register renaming  Instructions are fetched, decoded and issued in order  An instruction will only enter the ISSUE stage if it does not cause a WAR or WAW hazard  Only one instruction can be issued at a time, and in the case multiple instructions are ready, the oldest one will go first IF ID ISSUE ALU MEM FADD FADD FMUL WB Course on: Advanced Computer Architectures – Prof. C Silvano EXAM 30/06/2017 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) Page 2 - SOLUTION Fill in the following table pointing out, for each instruction, the pipeline stages activated in each clock cycle and type of hazards INSTRUCTION C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 Type of Haz ards lw $t1,VECTA($t6) IF ID IS ALU M1 M2 WB addi $t1,$t1,4 IF ID IS ALU WB WAW $t1 +RAW $t1 sw $t1,VECTA($t6) IF ID IS ALU M1 M2 WB R A W $ t 1 lw $t1,VECTB($t6) I F I D I S A L U M 1 M 2 W B WAW $t1 add WAR $t1 sw addi $t1,$t1,4 IF ID IS…