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Advanced Computer Architectures June 30, 2017 Prof. Donatella Sciuto Name Last Name POLIMI ID Number Problem 1 (6 points) Problem 2 (5 points) Problem 3 (5 points) Question 1 (5 points) Question 2 (6 points) Question 3 (5 points) Total (32 points) Problem 1 In this problem we will examine the execution of a code segment on the following single-issue out-of-order processor: You can assume that: • All functional units are pipelined • ALU operations take 1 cycle • Memory operations take 3 cycles (includes time in ALU) • The Write Back unit has a single write port • There is no register renaming • Instructions are fetched, decoded and issued in order • An instruction will only enter the ISSUE stage if it does not cause a WAR or WAW hazard • Only one instruction can be issued at a time, and in the case multiple instructions are ready, the oldest one will go first IF ID ISSUE ALU MEM FADD FADD FMUL WB Fill in the following table to indicate how the given code will execute. Assume all register values are available at the start of execution. INSTRUCTION C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 Type of Hazards lw $t1,VECTA($t6) addi $t1,$t1,4 sw $t1,VECTA($t6) lw $t1,VECTB($t6) addi $t1,$t1,4 sw $t1,VECTB($t6) Insert in the empty pipeline scheme the stalls needed to solve the previous data, control and structural hazards. INSTRUCTION C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 lw $t1,VECTA($t6) addi $t1,$t1,4 sw $t1,VECTA($t6) lw $t1,VECTB($t6) addi $t1,$t1,4 sw $t1,VECTB($t6) Fill in the following table pointing out the NUMBER OF STALLS to be inserted before (or during) each instruction to solve data, control or structural hazards. INSTRUCTION Type of Hazards Number of stalls lw $t1,VECTA($t6) addi $t1,$t1,4 sw $t1,VECTA($t6) lw…