Informazioni sul documento
- Università
- Politecnico di Milano
- Corso di laurea
- Computer Engineering
- Materia
- Digital Systems Design Methodologies
- Classificazione
- Esercizi · Divisi per argomento
- Formato originale
- Testo
- Testo ricercabile
Divisi per argomento di Digital Systems Design Methodologies per il corso di Computer Engineering presso Politecnico di Milano. Materiale proveniente dall’archivio storico Studwiz e classificato per la consultazione online.
Divisi per argomento di Digital Systems Design Methodologies per il corso di Computer Engineering presso Politecnico di Milano. Materiale proveniente dall’archivio storico Studwiz e classificato per la consultazione online.
Qualità dell’importazione: il testo è stato estratto direttamente dal documento originale.
Passaggi rappresentativi riconosciuti nelle diverse parti del materiale. Il testo completo resta presente nella pagina per la ricerca, mentre l’anteprima compatta rende più semplice la lettura.
KMS Exercise 1 Verify if the dashed path is a false path and eliminate it using the KMS technique. OUT 11 2 1 11 A B C Solution: OUT 11 2 1 11 A B C 1 1 0 0 1 1 0 0 1 Non-controlling values cannot be imposed, so the critical path can be removed. OUT 11 2 1 11 A B C 0 0 The transformed circuit is the following one 1 OUT 1 1 11 A B Exercise 2 Eliminate the dashed false path using the KMS technique. OUT1 OUT2 P6 P7 P5 P4 P3 P2 P1 A B C D Solution: OUT1 OUT2 P6 P7 P5 P4 P3A P3B P2 P1 A B C D 0 0 The transformed circuit is the following one 2 OUT1 OUT2 P6 P7 P4 P3B P2 P1 A B C D 3 Exercise 1: KMS Given the following circuit: eliminate the false paths (redundant parts of the circuit) using the KMS technique. Solution draft: We consider the topological critical path that starts from input C and verify if it is observable at the output. Thus we impose non-controlling values to the ports traversed by the path. If they are applicable it means that the path is really activated. Otherwise it can be removed. The values are shown in the following figure: Starting from port b, we impose the value 1 as non controlling for the port AND. Thus we have this value also on the second input of the port a and input B=1. Thus, to have E=0, as non controlling value for the port d, the first input of the port a (i.e., input A) has to be 0. Now, consider G=0 as non controlling value for port e. If A=0, it results that D=1. Therefore, port c has D=1 and B=1. This is not admissible, since to have G=0, at least one input has to be at 0. It means that non- controlling values cannot be imposed to that critical path (C is not observable at the output) and, thus, it can be removed. Finally, the resulting circuit is the following one, where the input C has been removed: As you can see, the circuit has…
Prima pagina del documento.