Informazioni sul documento
- Università
- Politecnico di Milano
- Corso di laurea
- Computer Engineering
- Materia
- Digital Systems Design Methodologies
- Classificazione
- Esercizi · Divisi per argomento
- Formato originale
- Testo
- Testo ricercabile
Divisi per argomento di Digital Systems Design Methodologies per il corso di Computer Engineering presso Politecnico di Milano. Materiale proveniente dall’archivio storico Studwiz e classificato per la consultazione online.
Divisi per argomento di Digital Systems Design Methodologies per il corso di Computer Engineering presso Politecnico di Milano. Materiale proveniente dall’archivio storico Studwiz e classificato per la consultazione online.
Qualità dell’importazione: il testo è stato estratto direttamente dal documento originale.
Passaggi rappresentativi riconosciuti nelle diverse parti del materiale. Il testo completo resta presente nella pagina per la ricerca, mentre l’anteprima compatta rende più semplice la lettura.
Timing Analysis Exercise 1 Identify the critical path, assumed that the required time is equal to 7. 2 2 2 1 0 2 1 1 3 2 2 2 Solution: 2 2 2 1 0 2 1 1 3 2 2 2 0 2 5 0 2 2 3 3 3 0 2 2 5 5 7 9 74 4 10 2 0 2 2 1 0 2 1 1 3 2 2 2 0/0 2/0 5/-1 0/-3 2/+1 2/-1 3/-1 3/+1 3/0 0/-3 2/-3 2/-3 5/-3 5/-1 7/-3 9/-3 7/-14/0 4/0 10/-3 1 2 0 2 2 1 0 2 1 1 3 2 2 2 0/0 2/0 5/-1 0/-3 2/+1 2/-1 3/-1 3/+1 3/0 0/-3 2/-3 2/-3 5/-3 5/-1 7/-3 9/-3 7/-14/0 4/0 10/-3 2 Exercise 1: timing analysis and critical path Given the following circuit: identify the critical path, assumed that the required time is equal to 7. Solution draft: The timing analysis is a methodology to analyze a circuit in order to identify the critical points from the timing point of view and drive specific optimization methods. To analyze the graph, the arrival time has to be computed for each node. The first simplified model introduced during the lecture will be adopted: Ai=max AkDi where Akare the arrival times of the nodes incoming to node i and Diis the related delay. The nodes are topologically ordered from the sources (directly connected to inputs) to the sinks (directly connected to outputs). A possible ordering is shown in the following figure (the black numbers near the nodes), as well as the resulting arrival times (the red numbers on the edges): Consider, for example, the node 11, directly connected to OUT and having a delay equals to 1. It has two incoming nodes, 9 a nd 10, that has, respectively, an arrival time equals to 7 and 9. The maximum arrival time is 9, the delay is 1 and, thus, the arrival time of node 11 is 10. This is also the arrival time of the whole circuit, since it is the time which the output result is available. Unfortunately, the arrival time is greater than the required time. It means that…
Prima pagina del documento.