06 05 2024 E S Silvano

Page 1

Surname Name POLIMI Personal code Signature SOLUTION Politecnico di Milano, 6 May 2024 Course on Advanced Computer Architectures Prof. C. Silvano EX 1 ( 4 points) EX 2 ( 5 points) EX 3 ( 4 points) QUIZ 4 ( 1 point) QUIZ 5 ( 1 point) TOTAL ( 15 points) QUIZ 6 OPTIONAL + 3 extra points Course on Advanced Computer Architectures EXAM 06/05/2024 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! Page 1 - SOLUTION EXERCISE 1: VLIW (4 points) Let’s consider the following assembly code: INIT: ADDUI $R1, $R0, 0 ADDUI $R2, $R0, 40 ADDUI $R4, $R0, 8 LOOP1: LD $F0, 0 ($R1) FADD $F4, $F0, $F2 SD $F4, 0 ($R1) ADDUI $R3, $R0, 0 LOOP2: LD $F6, 0($R3) FADD $F8, $F6, $F2 SD $F8, 0($R3) ADDUI $R3, $R3, 4 BNE $R3, $R4, LOOP2 ADDUI $R1, $R1, 4 BNE $R1, $R2, LOOP1 1. Complete the code of the first iteration of the outer loop LOOP1: LOOP1: LD $F0, 0 ($R1) FADD $F4, $F0, $F2 SD $F4, 0 ($R1) ADDUI $R3, $R0, 0 _____________________________ _____________________________ _____________________________ _____________________________ _____________________________ _____________________________ _____________________________ _____________________________ _____________________________ _____________________________ _____________________________ _____________________________ Course on Advanced Computer Architectures EXAM 06/05/2024 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! Page 2 - SOLUTION 2. Now schedule the first iteration of the outer loop LOOP1 by using the list-based scheduling (do NOT introduce any software pipelining, loop unrolling and modifications to loop indexes) on a 3-issue VLIW machine with fully pipelined functional units: • 1 Memory Unit with 2 cycle latency • 1 Integer ALU with 1 cycle latency to next Int/FP/LD/SD & 2 cycle latency to next Branch • 1 FP ALU with 2…