Full exam for Digital Systems Design Methodologies in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Politecnico di Milano Dipartimento di Elettronica e Informazione prof. Fabrizio Ferrandi Digital Systems Design Methodologies 2 – July 7th 2015 Polimi ID _______ _______________________ Surname _______ __________________ Name _____________________ This is a closed -book
Full exam for Digital Systems Design Methodologies in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Politecnico di Milano Dipartimento di Elettronica e Informazione prof. Fabrizio Ferrandi Digital Systems Design Methodologies 2 – July 7th 2015 Polimi ID _______ _______________________ Surname _______ __________________ Name _____________________ This is a closed -book
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Politecnico di Milano Dipartimento di Elettronica e Informazione prof. Fabrizio Ferrandi Digital Systems Design Methodologies 2 – July 7th 2015 Polimi ID _______ _______________________ Surname _______ __________________ Name _____________________ This is a closed -book examination. You cannot use computers, phones or laptops during the exam. Paper will be provided, but you should bring and use writing instruments that yield marks dark enough to be read easily. Erasable pens can be used. Total available time: 1h:30m. Exercise 1 (9 points) _________________________ Exercise 2 (7 points) _________________________ Exercise 3 (8 points) _________________________ Exercise 4 (3 points) _________________________ Exercise 5 (3 points) _________________________ Exercise 6 (3 points) _________________________ Digital Systems Design Methodologies 2 – July 7th 2015 2 /7 Exercise n. 1 Given the following circuit: Compute the test vector with Podem for the SA-1 fault given. Use the following backtrace procedure during the test vector generation: backtrace(s, vs) { v = vs; while (s is a gate output) { if (s is NAND or INVERTER or NOR) v = not(v); if (s requires setting all inputs) select unassigned input a of s with hardest controllability to value v; else select unassigned input a of s with easiest controllability to value v; s = a; } return (s, v) /* Gate and value to be assigned */; } Digital Systems Design Methodologies 2 – July 7th 2015 3 /7 Digital Systems Design Methodologies 2 – July 7th 2015 4 /7 Exercise n. 2 Given the following circuit: Compute the result of the deductive simulation obtained by applying this input vector A=1, B= 0, C=0, D=1, E=0 Digital Systems Design Methodologies 2 – July 7th 2015 5 /7 Exercise n. 3 Show if the two following circuits are equivalent…
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