Document information
- University
- Politecnico di Milano
- Degree programme
- Computer Engineering
- Subject
- Advanced Computer Architectures
- Academic year
- 2022-2023
- Classification
- Exam · Full exam
- Content
- Exam paper only
- Original format
- Text
- Searchable text
Full exam for Advanced Computer Architectures in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Surname Name POLIMI Personal code Signature Politecnico di Milano, 8 May 2023 Course on Advanced Computer Architectures Prof. C. Silvano EX 1 ( 4 points) EX 2 ( 4 points) EX 3 ( 3 points) EX 4 ( 2 points) QUIZ 5 ( 1 point) QUIZ 6 ( 1 point) TOTAL ( 15 points) EX 7 (optional) + 3
Full exam for Advanced Computer Architectures in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Surname Name POLIMI Personal code Signature Politecnico di Milano, 8 May 2023 Course on Advanced Computer Architectures Prof. C. Silvano EX 1 ( 4 points) EX 2 ( 4 points) EX 3 ( 3 points) EX 4 ( 2 points) QUIZ 5 ( 1 point) QUIZ 6 ( 1 point) TOTAL ( 15 points) EX 7 (optional) + 3
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Surname Name POLIMI Personal code Signature Politecnico di Milano, 8 May 2023 Course on Advanced Computer Architectures Prof. C. Silvano EX 1 ( 4 points) EX 2 ( 4 points) EX 3 ( 3 points) EX 4 ( 2 points) QUIZ 5 ( 1 point) QUIZ 6 ( 1 point) TOTAL ( 15 points) EX 7 (optional) + 3 extra points Course on Advanced Computer Architectures EXAM 08/05/2023 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! Page 1 EXERCISE 1: VLIW (4 points) Let’s consider the following FOR loop: FOR:LD $F2, A($R1) LD $F4, B($R1) LD $F6, C($R1) FADD $F2,$F2,$F2 SD $F2,B($R1) FADD $F4,$F4,$F4 SD $F4,C($R1) FADD $F6,$F6,$F6 SD $F6,D($R1) ADDUI $R1,$R1,4 BNE $R1,$R2, FOR Given a 4-issue VLIW machine with fully pipelined functional units: • 2 Memory Units with 2 cycle latency • 1 Integer ALU with 1 cycle latency to next Int/FP & 2 cycle latency to next Branch • 1 FP ALU with 3 cycle latency The branch is completed with 1 cycle delay slot (branch solved in ID stage). No branch prediction. In the Register File, it is possible to read and write at the same address at the same clock cycle. Considering one iteration of the loop, complete the following table by using the list-based scheduling (do NOT introduce any software pipelining, loop unrolling and modifications to loop indexes) on the 4-issue VLIW machine including the BRANCH DELAY SLOT. Please do not write in NOPs. Memory Unit 1 Memory Unit 2 Integer Unit Floating Point Unit C1 LD F2, A(R1) LD F4, B(R1) C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 Course on Advanced Computer Architectures EXAM 08/05/2023 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! Page 2 1. How long is the critical path? __________________________________ 2. What performance did you achieve in CPIas?…
First page of the document.