Full exam for Advanced Computer Architectures in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Problem 1 Assume that the following code has been executed on a CPU with SCOREBOARD. Instruction ISSUE READ OPERAND EXE COMPLETE WB I1 lw $1, 24($fp) 1 2 5 6 I2 lw $2, 8($fp) 2 3 6 7 I3 lw $3, 4($fp) 7 8 11 12 I4 add $2, $2, $3 8 13 16 17 I5 add $1, $1, $2 9 18 21 22 I6 sw $1,
Full exam for Advanced Computer Architectures in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Problem 1 Assume that the following code has been executed on a CPU with SCOREBOARD. Instruction ISSUE READ OPERAND EXE COMPLETE WB I1 lw $1, 24($fp) 1 2 5 6 I2 lw $2, 8($fp) 2 3 6 7 I3 lw $3, 4($fp) 7 8 11 12 I4 add $2, $2, $3 8 13 16 17 I5 add $1, $1, $2 9 18 21 22 I6 sw $1,
Import quality: text was extracted directly from the original document.
Representative passages recognised in different parts of the material. The full extracted text remains available to search, while this compact preview makes the page easier to read.
Problem 1 Assume that the following code has been executed on a CPU with SCOREBOARD. Instruction ISSUE READ OPERAND EXE COMPLETE WB I1 lw $1, 24($fp) 1 2 5 6 I2 lw $2, 8($fp) 2 3 6 7 I3 lw $3, 4($fp) 7 8 11 12 I4 add $2, $2, $3 8 13 16 17 I5 add $1, $1, $2 9 18 21 22 I6 sw $1, 16($fp) 10 23 26 27 A. List all the possible conflicts in the code. B. Is there a “configuration” that can respect the shown execution? How many units? Which kind? What latency? C. If the previous table was not correct, please write the right one and specify the number, kind, and latency for each unit. Answer 1.A Answer 1.B Yes, it exists. 2 LDU, 2 FPU (3cc latency for both kind of FUs) Answer 1.C Instruction ISSUE READ OPERAND EXE COMPLETE WB I1 lw $1, 24($fp) I2 lw $2, 8($fp) I3 lw $3, 4($fp) I4 add $2, $2, $3 I5 add $1, $1, $2 I6 sw $1, 16($fp) Problem 2 Please consider the program in the table to be executed on a CPU with dynamic scheduling based on TOMASULO. Consider an architecture with: • 3 RESERVATION STATIONS (RS1, RS2, RS3) + 2 LDU units (LDU1, LDU2) with latency 3 cycles • 2 RESERVATION STATIONS (RS4, RS5) + 2 FPU (FPU1, FPU2) with latency 3 cycles 1. Please complete the TOMASULO TABLE by assuming a cache MISS on I2 that adds 5 penalty cycles. Instruction ISSUE Start EXE WB I1 ld $1, 28($fp) 1 2 5 I2 ld $2, 16($fp) 2 3 11 I3 addd $1, $1, $2 3 12 15 I4 ld $2, 12($fp) 4 6 9 I5 addd $2, $1, $2 5 16 19 I6 addd $1, $1, 1 16 17 20 I7 sd $1, 0($2) 17 21 24 Problem 3 Describe (the answer has to be effectively supported) a 1-BHT and a 2-BHT able to execute the following assembly code (R0 is set to 4, R1 is set to 0) LOOP: LD F1 0 R0 ADDD F2 F1 F1 DIVD F3 F2 F1 ADDI R1 R1 1000 LOOP2: MULTD F12 F3 F2 SUBI R1 R1 1 BNEZ R1 LOOP2 SUBI R0 R0 4 BNEZ R0 LOOP The obtained result, in terms of miss…
First page of the document.
