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Politecnico di Milano, July 9, 2018 Course on Advanced Computer Architectures Prof. D. Sciuto, Prof. C. Silvano Surname (Cognome) Name (Nome) POLIMI ID Number Signature (Firma) Course on Advanced Computer Architectures EXAM 9/07/2018 – Please write by PEN in CAPITAL LETTERS & BLACK/BLUE!!! EXERCISE 1 – MULTI-CYCLE PIPELINE (5 points) In this problem we will examine the execution of the following code segment on the following single-issue out-of-order processor: ! •All functional units are pipelined •ALU operations take 1 clock cycle •Memory operations take 2 clock cycles (includes time in ALU) •FP ALU operations take 2 clock cycles •The Write Back unit has a single write port •There is no register renaming •Instructions are fetched, decoded and issued in order •An instruction will only enter the ISSUE stage if it does not cause a WAR or WAW hazard •Only one instruction can be issued at a time, and in the case multiple instructions are ready, the oldest one will go first Fill in the following table pointing out, for each instruction, the pipeline stages activated in each clock cycle and type of hazards: EX1 ( 5 points) EX2 ( 5 points) EX3 ( 6 points) Q1 ( 5 points) Q2 ( 5 points) SIX QUESTIONS ( 6 points) TOTAL (32 points) Instruction C 1 C2C3C4C5C6C7C8C9C1 0 C1 1 C1 2 Type of Hazards lw.d $f1,BASEA($r1) addi.d $f1,$f1,k1 add.d $f3,$f2,$f1 add.d $f1,$f2,$f3 Page !1 Course on Advanced Computer Architectures EXAM 9/07/2018 – Please write by PEN in CAPITAL LETTERS & BLACK/BLUE!!! Insert in the empty pipeline scheme the pipeline stages and stalls needed to solve the previous data, control and structural hazards. Fill in the following table pointing out the NUMBER OF STALLS to be inserted within each instruction to solve the hazards: sw.d $f1,BASEA($r1) IN S C 1 C2C 3 C4 C 5…