Document information
- University
- Politecnico di Milano
- Degree programme
- Computer Engineering
- Subject
- Advanced Computer Architectures
- Academic year
- 2024-2025
- Classification
- Exam · Full exam
- Content
- Exam paper only
- Original format
- Text
- Searchable text
Full exam for Advanced Computer Architectures in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Surname (COGNOME) Name POLIMI Personal Code Signature Politecnico di Milano, 11 February, 2025 Course on Advanced Computer Architectures Prof. C. Silvano EX1 ( 5 points) EX2 ( 3 points) EX3 ( 2 points) EX4 ( 5 points) Q1 ( 5 points) Q2 ( 5 points) QUIZZES ( 8 points) TOTAL (33
Full exam for Advanced Computer Architectures in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Surname (COGNOME) Name POLIMI Personal Code Signature Politecnico di Milano, 11 February, 2025 Course on Advanced Computer Architectures Prof. C. Silvano EX1 ( 5 points) EX2 ( 3 points) EX3 ( 2 points) EX4 ( 5 points) Q1 ( 5 points) Q2 ( 5 points) QUIZZES ( 8 points) TOTAL (33
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Surname (COGNOME) Name POLIMI Personal Code Signature Politecnico di Milano, 11 February, 2025 Course on Advanced Computer Architectures Prof. C. Silvano EX1 ( 5 points) EX2 ( 3 points) EX3 ( 2 points) EX4 ( 5 points) Q1 ( 5 points) Q2 ( 5 points) QUIZZES ( 8 points) TOTAL (33 points) Course on Advanced Computer Architectures – prof. C. Silvano EXAM 11 Feb. 2025 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! Page 1 EXERCISE 1 – DEPENDENCY ANALYSIS + TOMASULO (5 points) 1. Let’s consider the following assembly code containing multiple types of intra-loop dependences. Complete the following table by inserting all types of true-data-dependences, anti-dependences and output dependences for each instruction: I# TYPE OF INSTRUCTION ANALYSIS OF DEPENDECES: 1. True data dependence with I# for $Fx 2. Anti-dependence with I# for $Fy 3. Output-dependence with I# for $Fz I0 LOOP: LD $F0, A($R0) None I1 LD $F2, B($R0) None I2 FADD $F4, $F0, $F2 I3 FADD $F6, $F4, $F4 I4 SD $F4, C($R0) I5 SD $F6, D($R0) I6 ADDI $R0, $R0, 4 I7 BNE $R0, $R1, LOOP 2. Let’s consider the previous assembly code to be executed on a CPU with dynamic scheduling based on TOMASULO algorithm with all cache HITS, a single Common Data Bus and: • 2 RESERV. STATIONS (RS1, RS2) with 2 LOAD/STORE units (LDU1, LDU2) with latency 6 • 2 RESERVATION STATION (RS3, RS4) with 2 FP unit12 (FPU1, FPU2) with latency 2 • 1 RESERVATION STATION (RS5) with 1 INT_ALU/BR unit (ALU1) with latency 1 Please complete the following table: LOOP: LD $F0, A($R0) 1 2 8 None RS1 LDU1 LD $F2, B($R0) 2 3 9 None RS2 LDU2 FADD $F4, $F0, $F2 FADD $F6, $F4, $F4 SD $F4, C($R0) SD $F6, D($R0) ADDI $R0, $R0, 4 BNE $R0, $R1, LOOP Calculate the CPI =_____________________________________ Course on Advanced Computer Architectures – prof. C.…
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