13 06 2023 E T Silvano

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Surname (COGNOME) Name POLIMI Personal Code Signature Politecnico di Milano, 13 June, 2023 Course on Advanced Computer Architectures Prof. C. Silvano EX1 ( 5 points) EX2 ( 5 points) EX3 ( 5 points) Q1 ( 5 points) Q2 ( 5 points) QUIZZES ( 8 points) TOTAL (33 points) Course on Advanced Computer Architectures – prof. C. Silvano EXAM 13 June 2023 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! Page 1 EXERCISE 1 – TOMASULO (5 points) Let’s consider the following assembly code. to be executed on a CPU with dynamic scheduling based on TOMASULO algorithm with all cache HITS, a single Common Data Bus and: • 2 RESERVATION STATIONS (RS1, RS2) with 1 LOAD/STORE unit (LDU1) with latency 4 • 2 RESERVATION STATION (RS3, RS4) with 1 ALU/BR unit (ALU1) with latency 2 Please complete the following table: INSTRUCTION ISSUE START EXEC WRITE RESULT Hazards Type RSi UNIT I1: lw $f0,0($r1) 1 2 6 RS1 LDU1 I2: lw $f2,4($r1) 2 RS2 LDU1 I3: lw $f4,8($r1) I4: lw $f6,C($r1) I5:fadd $f8,$f0,$f2 I6:fadd $f10,$f4,$f6 I7:fadd $f10,$f8,$f10 I8: sw $f10,0($r1) Calculate the CPI: CPI = _______________________________________________________________ Course on Advanced Computer Architectures – prof. C. Silvano EXAM 13 June 2023 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! Page 2 EXERCISE 2 – MESI PROTOCOL (5 points) Let’s consider the following access patterns on a 4-processor system with a direct-mapped, write-back cache with one cache block per processor and a two-cache block memory. Assume the MESI protocol is used, with write-back caches, write-allocate, and write-invalidate of other caches. Please complete the following table: Cycle After Operation P0 cache block state P1 cache block state P2 cache block state P3 cache block state Memory at bl. 0 up to date? Memory at bl. 1 up…