15 07 2024 E TS Pilato

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Dipartimento di Elettronica e Informazione Politecnico di Milano 20133 Milano (Italia) Piazza Leonardo da Vinci, 32 Tel. (+39) 02-2399.3400 Fax (+39) 02-2399.3411 Advanced Computer Architectures July 15, 2024 Prof. Christian Pilato Name Last Name ID Number Problem 1 (20%) Problem 2 (15%) Problem 3 (15%) Question 1 (15%) Question 2 (20%) Question 3 (15%) Total (100%) NOTE: students have 90’ to complete the exam. To pass the exam, a minimum score of 25% is requested by each “section” (section 1: problems, section 2: questions). Problem 1 Assume that the following code has been executed on a CPU with SCOREBOARD. Instruction ISSUE READ OPERAND EXE COMPLETE WB I1 lw $1, 36($fp) 1 2 5 6 I2 lw $3, 8($fp) 2 3 6 7 I3 lw $4, 64($fp) 3 4 7 8 I4 lw $2, 20($fp) 4 5 8 9 I5 sub $3, $2, $3 5 10 11 12 I6 multdd $f0, $1, $4 6 9 19 20 I7 addd $f1, $f1, $f0 7 21 25 26 I8 sd $f1, $3(fp) 10 27 30 31 A. List all the possible conflicts in the code. B. Is there a “configuration” that can respect the shown execution? How many units? Which kind? What latency? C. If the previous table was not correct, please, write the right one and specify the number, kind and latency for each unit. Answer 1.A Answer 1.B Answer 1.C A possible solution (NOT THE UNIQUE) is Scoreboard with the following FUs: 4 LDU (3 cc latency), 1 ALU (1cc latency), 1 MUL (10 cc latency), 1 FPU (4 cc latency) Instruction ISSUE READ OPERAND EXE COMPLETE WB I1 lw $1, 36($fp) 1 2 5 6 I2 lw $3, 8($fp) 2 3 6 7 I3 lw $4, 64($fp) 3 4 7 8 I4 lw $2, 20($fp) 4 5 8 9 I5 sub $3, $2, $3 8 10 11 12 I6 multdd $f0, $1, $4 9 10 20 21 I7 addd $f1, $f1, $f0 10 22 26 27 I8 sd $f1, $3(fp) 11 28 31 32 Problem 2 In this problem, you will port code to a simple 4-issue VLIW machine, and schedule it to improve performance. Details about the 4-issue VLIW…