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Full exam for Advanced Computer Architectures in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Course on Advanced Computer Architectures Surname (Cognome) SOLUTION Name (Nome) POLIMI ID Number Signature (Firma) Politecnico di Milano, July 18th, 2017 Prof. C. Silvano EX1 ( 5 points) EX2 ( 6 points) EX3 ( 5 points) Q1 ( 5 points) Q2 ( 6 points) Q3 ( 5 points) TOTAL (32

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Full exam for Advanced Computer Architectures in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Course on Advanced Computer Architectures Surname (Cognome) SOLUTION Name (Nome) POLIMI ID Number Signature (Firma) Politecnico di Milano, July 18th, 2017 Prof. C. Silvano EX1 ( 5 points) EX2 ( 6 points) EX3 ( 5 points) Q1 ( 5 points) Q2 ( 6 points) Q3 ( 5 points) TOTAL (32

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Course on Advanced Computer Architectures Surname (Cognome) SOLUTION Name (Nome) POLIMI ID Number Signature (Firma) Politecnico di Milano, July 18th, 2017 Prof. C. Silvano EX1 ( 5 points) EX2 ( 6 points) EX3 ( 5 points) Q1 ( 5 points) Q2 ( 6 points) Q3 ( 5 points) TOTAL (32 points) Course on: Advanced Computer Architectures – Prof. C Silvano EXAM 18/07/2017 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) Page 1 - SOLUTION EXERCISE 1 – PIPELINE OPTIMIZATIONS for VLIW (5 points) Consider the following program in C code and MIPS Assembly Code to be executed on a 3-issue MIPS VLIW architecture including the following optimizations:  RF read and write at the same address in the same clock cycle  Full Forwarding Paths  Computation of PC and TARGET ADDRESS for branch & jump instructions anticipated in the ID stage  Static Branch Prediction ALWAYS TAKEN with Branch Target Buffer C Code: Assembly Code: for(int i=0; i<N; i++) C[i] = A[i]*A[i] + B[i]; for: ld $f1, 0($r1) ld $f2, 0($r2) fmul $f1, $f1, $f1 fadd $f1, $f1, $f2 st $f1, 0($r3) addi $r1, $r1, 4 addi $r2, $r2, 4 addi $r3, $r3, 4 bne $r3, $r4, for Consider to have in the 3-issues VLIW: 1 ALU/BRANCH UNIT + 1 LOAD/STORE UNIT + 1 Floating Point UNIT with the following pipeline stages: 1 A/B IF ID EX WB 1 L/S IF ID EX ME WB 1 FPU IF ID EX1 EX2 WB 1. Complete the pipeline scheme by RESCHEDULING the program and inserting the NOPS where needed 2. Please add in the last column the Forwarding paths used Course on: Advanced Computer Architectures – Prof. C Silvano EXAM 18/07/2017 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) Page 2 - SOLUTION Num. Stalls INSTRUCTION C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 Forwarding Path 1 A/B for:addi…

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