20 01 2025 E T Pilato

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Dipartimento di Elettronica e Informazione Politecnico di Milano 20133 Milano (Italia) Piazza Leonardo da Vinci, 32 Tel. (+39) 02-2399.3400 Fax (+39) 02-2399.3411 Advanced Computer Architectures January 20, 2025 Prof. Christian Pilato Name Last Name ID Number Problem 1 (20%) Problem 2 (15%) Problem 3 (15%) Question 1 (15%) Question 2 (20%) Question 3 (15%) Total (100%) NOTE: students have 90’ to complete the exam. To pass the midterm, a minimum score of 25% is requested by each “section” (section 1: problems, section 2: questions). The overall score to access the oral has to be greater or equal to 50% Problem 1 Consider the following access pattern on a two- processor system with a direct - mapped, write-back cache with one cache block and a two cache block memory. Assume the MESI protocol is used, with write-back caches, write-allocate, and write-invalidate of other caches. Time After Operation Px cache block state Py cache block state Pz cache block state Memory at Block 0 up to date? Memory at Block 1 up to date? Memory at Block 2 up to date? 1 Px read block 0 Exclusive (0) Invalid Modified (2) yes yes no 2 Py write block 2 3 Px read block 2 4 Pz read block 0 5 Pz write block 2 6 Px read block 2 7 Py read block 2 8 Pz write block 2 9 Px write block 1 10 Py read block 1 Problem 2 Describe (the answer has to be effectively supported) a 1-BHT and a 2-BHT able to execute the following assembly code (R0 is set to 4, R1 is set to 1) LOOP: LD F1 0 R0 ADDD F2 F1 F1 DIVD F3 F2 F1 ADDI R1 R1 1000 LOOP2: MULTD F12 F3 F2 SUBI R1 R1 2 BNEZ R1 LOOP2 SUBI R0 R0 4 BNEZ R0 LOOP The obtained result, in terms of miss predictions, is inline with theoretical characteristics of the two predictors? Please effectively support your answer. Answer Problem 3 Assume that the following code has…