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20 01 2025 E T Silvano

Full exam for Advanced Computer Architectures in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Surname (COGNOME) Name POLIMI Personal Code Signature Politecnico di Milano, 20 January, 2025 Course on Advanced Computer Architectures Prof. C. Silvano EX1 ( 5 points) EX2 ( 5 points) EX3 ( 5 points) Q1 ( 5 points) Q2 ( 5 points) QUIZZES ( 8 points) TOTAL (33 points) Course on

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Full exam for Advanced Computer Architectures in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Surname (COGNOME) Name POLIMI Personal Code Signature Politecnico di Milano, 20 January, 2025 Course on Advanced Computer Architectures Prof. C. Silvano EX1 ( 5 points) EX2 ( 5 points) EX3 ( 5 points) Q1 ( 5 points) Q2 ( 5 points) QUIZZES ( 8 points) TOTAL (33 points) Course on

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Surname (COGNOME) Name POLIMI Personal Code Signature Politecnico di Milano, 20 January, 2025 Course on Advanced Computer Architectures Prof. C. Silvano EX1 ( 5 points) EX2 ( 5 points) EX3 ( 5 points) Q1 ( 5 points) Q2 ( 5 points) QUIZZES ( 8 points) TOTAL (33 points) Course on Advanced Computer Architectures – prof. C. Silvano EXAM 20 Jan. 2025 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! Page 1 EXERCISE 1 – DEPENDENCY ANALYSIS + TOMASULO (5 points) 1. Let’s consider the following assembly code containing multiple types of intra-loop dependences. Complete the following table by inserting all types of true-data-dependences, anti-dependences and output dependences for each instruction: I# TYPE OF INSTRUCTION ANALYSIS OF DEPENDECES: 1. True data dependence with I# for $Fx 2. Anti-dependence with I# for $Fy 3. Output-dependence with I# for $Fz I0 LD $F2, A($R3) None I1 FADD $F2, $F2, $F4 I2 ADD $R1, $R2, $R2 I3 SD $F2, A($R1) I4 ADD $R2, $R1, $R1 I5 FADD $F4, $F2, $F4 I6 SD $F4, A($R2) Let’s consider the previous assembly code to be executed on a CPU with dynamic scheduling based on TOMASULO algorithm with all cache HITS, a single Common Data Bus and: • 2 RESERV. STATIONS (RS1, RS2) with 2 LOAD/STORE units (LDU1, LDU2) with latency 4 • 2 RESERVATION STATION (RS3, RS4) with 2 FP unit12 (FPU1, FPU2) with latency 3 • 1 RESERVATION STATION (RS5) with 1 INT_ALU/BR unit (ALU1) with latency 1 Please complete the following table: INSTRUCTION ISSUE START EXEC WRITE RESULT Hazards Type RSi UNIT I0: LD $F2, A($R3) 1 2 6 None RS1 LDU1 I1 FADD $F2, $F2, $F4 I2: ADD $R1, $R2, $R2 I3: SD $F2, A($R1) I4: ADD $R2, $R1, $R1 I5: FADD $F4, $F2, $F4 I6: SD $F4, A($R2) Calculate the CPI = _______________________________________ Course on Advanced Computer Architectures – prof. C.…

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