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22 01 2024 E T Silvano

Full exam for Advanced Computer Architectures in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Surname (COGNOME) Name POLIMI Personal Code Signature Politecnico di Milano, 22 January, 2024 Course on Advanced Computer Architectures Prof. C. Silvano EX1 ( 5 points) EX2 ( 4 points) EX3 ( 3 points) EX4 ( 3 points) Q1 ( 5 points) Q2 ( 5 points) QUIZZES ( 8 points) TOTAL (33

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Full exam for Advanced Computer Architectures in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Surname (COGNOME) Name POLIMI Personal Code Signature Politecnico di Milano, 22 January, 2024 Course on Advanced Computer Architectures Prof. C. Silvano EX1 ( 5 points) EX2 ( 4 points) EX3 ( 3 points) EX4 ( 3 points) Q1 ( 5 points) Q2 ( 5 points) QUIZZES ( 8 points) TOTAL (33

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Surname (COGNOME) Name POLIMI Personal Code Signature Politecnico di Milano, 22 January, 2024 Course on Advanced Computer Architectures Prof. C. Silvano EX1 ( 5 points) EX2 ( 4 points) EX3 ( 3 points) EX4 ( 3 points) Q1 ( 5 points) Q2 ( 5 points) QUIZZES ( 8 points) TOTAL (33 points) Course on Advanced Computer Architectures – prof. C. Silvano EXAM 22 Jan. 2024 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! Page 1 EXERCISE 1 – Tomasulo (5 points) Please consider the following assembly code: I1: lw $t2,VECTA($t6) I2: lw $t3,VECTB($t6) I3: lw $t4,VECTC($t6) I4: addi $t2,$t2,k I5: sw $t2,VECTA($t6) I6: add $t3,$t2,$t3 I7: add $t4,$t3,$t4 I8: sw $t4,VECTC($t6) to be executed on a CPU with dynamic scheduling based on TOMASULO algorithm with all cache HITS, a single Common Data Bus and: • 4 RESERVATION STATIONS (RS1, RS2, RS3, RS4) for 2 LOAD/STORE unit (LDU1, LDU2) with latency 6 • 2 RESERVATION STATIONS (RS5, RS6) for 2 ALU/BR FUs (ALU1, ALU2) with latency 2 1. Please complete the following table: I6: add $t3,$t2,$t3 I7: add $t4,$t3,$t4 2. Calculate the CPI: CPI = _______________________________________________________________ EXERCISE 2 on REORDER BUFFER (4 points) Let’s consider the following assembly code: I0: LD $F6, VECTA ($R1) I1: LD $F4, VECTB ($R1) I2: ADDD $F6, $F6, $F8 I3: SUBD $F4, $F4, $F8 I4: SD $F6, VECTA ($R1) I5: SD $F4, VECTB ($R1) executed by the Speculative Tomasulo architecture with an 8-entry ROB and: § 4 load buffers (Load1, Load2, Load3, Load4); § 2 FP RS (FP1, FP2) § 2 Integer RS (Int1, Int2) Course on Advanced Computer Architectures – prof. C. Silvano EXAM 22 Jan. 2024 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! Page 2 § Please update the following ROB and Rename Tables until the ROB becomes full and I0 is still in…

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First page: 22 01 2024 E T Silvano