Full exam for Digital Systems Design Methodologies in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Politecnico di Milano Dipartimento di Elettronica, Informazione e Bioingegneria prof. Fabrizio Ferrandi Digital Systems Design Methodologies 1 – September 26th 2016 Polimi ID _______ _______________________ Surname _______ __________________ Name _____________________ This is
Full exam for Digital Systems Design Methodologies in the Computer Engineering degree programme at Politecnico di Milano. The document covers: Politecnico di Milano Dipartimento di Elettronica, Informazione e Bioingegneria prof. Fabrizio Ferrandi Digital Systems Design Methodologies 1 – September 26th 2016 Polimi ID _______ _______________________ Surname _______ __________________ Name _____________________ This is
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Politecnico di Milano Dipartimento di Elettronica, Informazione e Bioingegneria prof. Fabrizio Ferrandi Digital Systems Design Methodologies 1 – September 26th 2016 Polimi ID _______ _______________________ Surname _______ __________________ Name _____________________ This is a closed -book examination. You cannot use computers, phones or laptops during the exam. Paper will be provided, but you should bring and use writing instru ments that yield marks dark enough to be read easily. Erasable pens can be used. Total available time: 1h:45m. Exercise 1 (5 points) _________________________ Exercise 2 (6 points) _________________________ Exercise 3 (6 points) _________________________ Exercise 4 (5 points) _________________________ Exercise 5 (6 points) _________________________ Exercise 6 (5 points) _________________________ Digital Systems Design Methodologies 1 – September 26th 2016 2 /12 Exercise n. 1 Given the following circuit: 1) Compute the smallest clock period Tmax such that retiming has not to be applied 2) Apply the retiming with T= Tmax-1 Digital Systems Design Methodologies 1 – September 26th 2016 3 /12 Digital Systems Design Methodologies 1 – September 26th 2016 4 /12 Exercise n. 2 Given the following circuit: where the delay of the OR and AND gates is equal to 2, while the delay of the inverters is equal to 1. a) Compute the circuit delay given these values applied to the inputs: A=1, B=0, C=1, D=1. b) Check with the proper algorithm if the output OUT is stable at time T=7 Digital Systems Design Methodologies 1 – September 26th 2016 5 /12
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