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Surname (Cognome) SOLUTION Name (Nome) POLIMI ID Number Signature (Firma) Politecnico di Milano, June 27, 2019 Course on Advanced Computer Architectures Prof. D. Sciuto, Prof. C. Silvano EX1 ( 5 points) EX2 ( 6 points) EX3 ( 5 points) Q1 ( 6 points) Q2 ( 4 points) SIX QUESTIONS ( 6 points) TOTAL (32 points) Course on Advanced Computer Architectures EXAM 27/06/2019 – Please write by PEN in CAPITAL LETTERS & BLACK/BLUE!!! Page 1 - SOLUTION EXERCISE 1 – MULTI-CYCLE PIPELINE (5 points) In this problem we will examine the execution of the following code segment on the following single-issue out-of-order processor:  All functional units are pipelined  ALU operations take 1 clock cycle  Memory operations take 2 clock cycles (includes time in ALU)  FP ADD operations take 2 clock cycles  The Write Back unit has a single write port  There is no register renaming  Instructions are fetched, decoded and issued in order  An instruction will only enter the ISSUE stage if it does not cause a WAR or WAW hazard  Only one instruction can be issued at a time, and in the case m ultiple instructions are ready, the oldest one will go first  Register File Read in ISSUE stage  Simultaneous read and write operations in the Register File at the same address Fill in the following table pointing out, for each instruction, the pipeline stages activated in each clock cycle and type of hazards: I1 lw.d $f2,BASEA($r1) I2 addi.d $f2,$f2,INC1 I3 sw.d $f2,BASEB($r1) I4 lw.d $f3,BASEC($r2) I5 sw.d $f3,BASED($r2) Instruction C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 Type of Hazards lw.d $f2,BASEA($r1) IF ID IS ALU ME WB addi.d $f2,$f2,INC1 IF ID IS ALU1 ALU2 WB WAW $f2, RAW $f2 sw.d $f2,BASEB($r1) IF ID IS ALU ME WB RAW $f2 lw.d $f3,BASEC($r2) IF ID IS ALU ME WB sw.d $f3,BASED($r2) IF ID IS ALU ME WB RAW…