28 04 2025 E T Santambrogio

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Advanced Computer Achitecture High Performance Processors and Systems April 28, 2025 Prof. Marco D. Santambrogio Name Last Name ID Number Question 1 (20%) Question 2 (20%) Problem 1 (30%) Problem 2 (30%) Total (100%) To pass the midterm, a minimum score of 20% is requested by each “section” (section 1: problems, section 2: questions). The overall score, to consider the midterm as passed to access the project, has to be greater or equal to 50% Question 1 (write your answer on the paper) Define the main characteristics of a VLIW architecture. Explain which is the basic idea behind Trace Scheduling for VLIW and why is it necessary to get good performance from a VLIW? Question 2 (write your answer on the paper) Using the “Early Evaluation of PC” applied to branch instructions, how many stalls are needed to execute the following assembly code. Effectively support your answer lw $1, 0($5) beq $1, $0, label Circle the bullet of the right answer • Answer 1: 1 • Answer 2: 2 • Answer 3: 0 • Answer 4: 3 Answer Answer 2 is the TRUE one. If a comparison register is a destination of immediately preceding load instruction 2 stall cycles are needed, the data to be stored in $1 is available after the MEM stage (lw) and needed in the ID stage. Problem 1 Assume that the following code has been executed on a CPU with TOMASULO with the following configuration: • 2 RS (RS1, RS2) with 2 MUL unit and 10 CC of latency • 2 RS (RS3, RS4) 2 ADDD/SUBD unit and 1 CC of latency • 1 RS (RS5) 1 LDU and 2 CC of latency Instruction ISSUE Start EXE WB I1 LD F1, 0 (R2) 1 2 4 I2 MULTD F2, F1, F1 2 5 15 I3 ADDD F3, F1, F5 5 5 6 I4 MULTD F2, F3, F1 4 7 17 I5 SUBD F5, F1, F5 3 6 7 A. List all the possible conflicts in the code. B. Is the proposed table correct? If it is not correct, please, write the right…