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- University
- Politecnico di Milano
- Degree programme
- Computer Engineering
- Subject
- Advanced Computer Architectures
- Academic year
- 2021-2022
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- Exam · Full exam
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29 06 2022 E TS Silvano
Full exam for Advanced Computer Architectures in the Computer Engineering degree programme at Politecnico di Milano. The document covers: NAME SURNAME PERSONAL CODE ACA2022_EXAM_FORM2 Data: 29/06/2022 1 ACA2022_FORM2_29June2022_SILVANO ACA Course -- Prof. SILVANO FORM2 is composed of 6 QUESTIONS to get UP TO 12 POINTS Duration is 24 minutes! Question 1 (complete table format) 2 points Let’s consider the following
Advanced Computer ArchitecturesFull exam
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Full exam for Advanced Computer Architectures in the Computer Engineering degree programme at Politecnico di Milano. The document covers: NAME SURNAME PERSONAL CODE ACA2022_EXAM_FORM2 Data: 29/06/2022 1 ACA2022_FORM2_29June2022_SILVANO ACA Course -- Prof. SILVANO FORM2 is composed of 6 QUESTIONS to get UP TO 12 POINTS Duration is 24 minutes! Question 1 (complete table format) 2 points Let’s consider the following
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NAME SURNAME PERSONAL CODE ACA2022_EXAM_FORM2 Data: 29/06/2022 1 ACA2022_FORM2_29June2022_SILVANO ACA Course -- Prof. SILVANO FORM2 is composed of 6 QUESTIONS to get UP TO 12 POINTS Duration is 24 minutes! Question 1 (complete table format) 2 points Let’s consider the following access patterns on a 4-processor system with a direct-mapped, write-back cache with one cache block per processor and a two-cache block memory. Assume the MESI protocol is used, with write-back caches, write-allocate, and write-invalidate of other caches. Please COMPLETE the following table: Cycle After Operation P0 cache block state P1 cache block state P2 cache block state P3 cache block state Memory at bl. 0 up to date? Memory at bl. 1 up to date? 0 Initial state Invalid Invalid Invalid Invalid Yes Yes 1 P0: Read Bl. 1 Excl (1) Invalid Invalid Invalid Yes Yes 2 P2: Read Bl. 0 Excl (1) Invalid Excl (0) Invalid Yes Yes 3 P1: Read Bl. 0 4 P3: Write Bl. 0 5 P0: Write Bl. 1 6 P2: Write Bl. 1 7 P1: Read Bl. 0 NAME SURNAME PERSONAL CODE ACA2022_EXAM_FORM2 Data: 29/06/2022 2 Feedback Cycle After Operation P0 cache block state P1 cache block state P2 cache block state P3 cache block state Memory at bl. 0 up to date? Memory at bl. 1 up to date? 0 Initial state Invalid Invalid Invalid Invalid Yes Yes 1 P0: Read Bl. 1 Excl (1) Invalid Invalid Invalid Yes Yes 2 P2: Read Bl. 0 Excl (1) Invalid Excl (0) Invalid Yes Yes 3 P1: Read Bl. 0 Excl (1) Shared (0) Shared (0) Invalid Yes Yes 4 P3: Write Bl. 0 Excl (1) Invalid Invalid Mod (0) No Yes 5 P0: Write Bl. 1 Mod (1) Invalid Invalid Mod (0) No No 6 P2: Write Bl. 1 Invalid Invalid Mod (1) Mod (0) No No 7 P1: Read Bl. 0 Invalid Shared (0) Mod (1) Shared (0) Yes No See MESI protocols on the slides on L13: Multiprocessors. NAME SURNAME PERSONAL CODE…
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