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Course on Advanced Computer Architectures Surname (Cognome) SOLUTION Name (Nome) POLIMI ID Number Signature (Firma) Politecnico di Milano, January 31st, 2018 Prof. D. Sciuto Prof. C. Silvano EX1 ( 6 points) EX2 ( 7 points) EX3 ( 3 points) Q1 ( 6 points) Q2 ( 5 points) Q3 ( 5 points) TOTAL (32 points) Course on: Advanced Computer Architectures – Prof. C Silvano EXAM 31/01/2018 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) Page 1 - SOLUTION EXERCISE 1 – MULTI-CYCLE PIPELINE (6 points) In this problem we will examine the execution of the following code segment on the following single-issue out-of-order processor: for (i = 0; i != N; i++) FOR:beq $t6,$t7,END { lw $t2,VECTB($t6) VECTB[i] = VECTB[i] + k1 + k2; addi $t2,$t2,k1 } addi $t2,$t2,k2 sw $t2,VECTB($t6) addi $t6, $t6,4 blt $t6,$t7,FOR Course on: Advanced Computer Architectures – Prof. C Silvano EXAM 31/01/2018 – Please write in CAPITAL LETTERS AND BLACK/BLUE COLORS!!! (MAIUSCOLO e COLORE NERO/BLU!!!) Page 2 - SOLUTION You can assume that: • All functional units are pipelined • ALU operations take 1 cycle • Memory operations take 3 cycles (includes time in ALU) • The Write Back unit has a single write port • There is no register renaming • Instructions are fetched, decoded and issued in order • An instruction will only enter the ISSUE stage if it does not cause a WAR or WAW hazard • Only one instruction can be issued at a time, and in the case multiple instructions are ready, the oldest one will go first • Program Counter calculation for conditional and unconditional branches is anticipated in the ISSUE stage • No Branch Prediction and no Branch Target Buffer • No simultaneous Read and Write in the Register File at the same address Fill in the following table pointing out,…