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- Politecnico di Milano
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- Computer Engineering
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- Digital Systems Design Methodologies
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- Exercises · By topic
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ExercisesBy topic
SAT analysis
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Digital Systems Design MethodologiesBy topic
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SAT-based false path analysis Exercise 1 Is the circuit stable at T=4? OUT 12 2 1 11 A B C D E F G H Solution: OU T(1, T = 4) = G(1, T = 3)∪ H(1, T = 3) =[B(1, T = 2)∩ D(1, T = 2)]∪ [E(1, T = 1)∪ F (1, T = 1)] =[B(1, T = 2)∩ A(0, T = 1)]∪ [[A(1, T = 0)∩ B(1, T = 0)]∪ [B(1, T =−1)∩ C(1, T =−1)]] =[B(1, T = 2)∩ A(0, T = 1)]∪ [[A(1, T = 0)∩ B(1, T = 0)]∪∅ ] =AB + AB =B OU T(1, T =∞) =AB + AB + BC =B OU T(1, T =∞)·!OU T(1, T = 4) = B· B =0 The output is stable at high value when T=4 OU T(0, T = 4) = G(0, T = 3)∩ H(0, T = 3) =[B(0, T = 2)∪ D(0, T = 2)]∩ [E(0, T = 1)∩ F (0, T = 1)] =[B(0, T = 2)∪ A(1, T = 1)]∩ [[A(0, T = 0)∪ B(0, T = 0)]∩ [B(0, T =−1)∪ C(0, T =−1)]] =[B(0, T = 2)∪ A(1, T = 1)]∩ [[A(0, T = 0)∪ B(0, T = 0)]∩∅ =∅ OU T(0, T =∞) =[B + A]· [A + B]· [B + C] =B· [B + C] =B 1 OU T(0, T =∞)!OU T(0, T = 4) = B· 1 ̸=0 The output is not stable at low value when T=4, so the circuit is not stable at T=4. 2
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